Високопродуктивний синхронізований матричний  процесор множення АЛП суперкомп’ютерів

Yaroslav Nykolaychuk; Volodymyr Hryha; Oleh Zastavnyi

Yaroslav Nykolaychuk д. т. н., професор, Західноукраїнський національний університет, вул. Львівська, 11, 46009, Тернопіль
Volodymyr Hryha к. т. н., доцент, Прикарпатський національний університет імені Василя Стефаника, вул. Шевченка, 57, 76018, Івано-Франківськ
Oleh Zastavnyi к.т.н., старший викладач, Західноукраїнський національний університет, вул. Львівська, 11, 46009, Тернопіль

Abstract

The scope of application and priority directions of improvement of high-performance multibit matrix multipliers (MMM) as components of ALU coprocessors of multicore supercomputers are outlined. The characteristics of performance and hardware complexity of known matrix multipliers are systematized. The prospect of improving the structures of multipliers based on synchronized single-bit accumulative binary adders (SABA) is substantiated. The algorithm and structure of the MMM based on multiplex-switched SABAs are proposed. The system characteristics of this class of multipliers are investigated depending on the bit depth of the input binary codes.

References

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High-performance synchronized matrix ALU multiplication processor for supercomputers

Abstract

References