Multi-bit subtraction operation in a parallel computational model

Fìz.-mat. model. ìnf. tehnol. 2021, 33:165-169

  • Andrii Tereshchenko V. M. Glushkov Institute of Cybernetics of NAS of Ukraine, Glushkova Str., 40, 03187, Kyiv
DOI: https://doi.org/10.15407/fmmit2021.33.165
Keywords: multi-bit arithmetic, multi-bit subtraction, carry sign, parallel computational model

Abstract

The paper proposes a new method for implementing the parallel multidigit subtraction. The paper provides an analysis on the basis of which it is possible to predict carry signs between words and between groups of words into which multidigit numbers are split on the substracting. The analysis is presented in the form of a lemma. The paper presents an iterative bitwise operation for correcting carry signs for each word in a group of words. An algorithm for implementation the substraction operation using k processors is proposed.

References
  1. McGeoch, C. C. (1993). Parallel Addition, The American Mathematical Monthly, 100(9), (Nov., 1993), 867-871. http://www.jstor.org/stable/2324666.
    DOI https://doi.org/10.1080/00029890.1993.11990504
  2. Tereshchenko, A., Zadiraka, V. (2018). Parallelnoe slozhenie na osnove vektornyih operatsiy Iskusstvennyiy intellekt, 2, 122–137. http://dspace.nbuv.gov.ua/handle/123456789/162381
Published
2021-09-06
How to Cite
Tereshchenko, A. (2021). Multi-bit subtraction operation in a parallel computational model. PHYSICO-MATHEMATICAL MODELLING AND INFORMATIONAL TECHNOLOGIES, (33), 165-169. https://doi.org/10.15407/fmmit2021.33.165
Issue
No 33 (2021): Physico-mathematical modeling and informational technologies, 2021, Issue 33
Section
Articles

Copyright (c) 2021 Andrii Tereshchenko (Автор)

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