Multi-bit structure improvement methods for multiplier devices of matrix type

Fìz.-mat. model. ìnf. tehnol. 2021, 32:80-85

  • Natalia Vozna West Ukrainian National University 11 Lvivska Str. (WUNU Building 1) Ternopil, 46009
  • Yaroslav Nykolaychuk Separated structural unit "Nadvirna Professional College of National Transport University"
  • Alina Davletova West Ukrainian National University 11 Lvivska Str. (WUNU Building 1) Ternopil, 46009
Keywords: multi-digit multipliers, structural complexity, speed

Abstract

The article proposes methods for improving the structures of matrix multipliers of multi-digit numbers. Advanced single-bit total adders with paraphrase switched inputs and paraphrase outputs are used, intended as components of high-speed matrix multipliers. Based on the use of such single-bit adders, the structures of matrix multipliers are proposed, characterized by 2 times increased speed, 5 times reduced structural complexity compared to known multipliers based on classical single-bit adders. Optimization of structures of multi-bit matrix multipliers is offered. Comparative estimates of structural and temporal complexities of their circuit implementations depending on the bit size of multiplied binary numbers are given. The use of optimized circuit solutions of matrix multipliers can significantly improve the system characteristics of complex computing devices with many such components in the crystals of microelectronic technologies.

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Published
2021-07-07
How to Cite
Vozna, N., Nykolaychuk, Y., & Davletova, A. (2021). Multi-bit structure improvement methods for multiplier devices of matrix type. PHYSICO-MATHEMATICAL MODELLING AND INFORMATIONAL TECHNOLOGIES, (32), 80-85. https://doi.org/10.15407/fmmit2021.32.080